CY82C693UB Datasheet, PDF (125/164 Pages) Cypress Semiconductor – hyperCache TM / Stand-Alone PCI Peripheral Controller with USB

PRELIMINARY
CY82C693UB
Register 12: Primary IDE Control Register (Read/Write) − Index=40H with a 32-bit access
Bit
Function
31:18
Reserved
17
16
15:14
13
12:11
10
9
8
7:6
5:4
3:2
1:0
Reserved
Reserved
Reserved
Retry I/O Accesses Not Completed by 16 PCI Clocks Control:
0:
I/O Accesses Not Completed by 16 PCI Clocks will not be retried.
1:
I/O Accesses Not Completed by 16 PCI Clocks will be retried.
Reserved
Slave Drive Prefetch Control:
0:
Disable Prefetch (Must be 0 for CDROM accesses).
1:
Enable Prefetch
Post Write Control:
0:
One level FIFO for Posted Writes
1:
Four levels of FIFO for Posted Writes
Master Drive Prefetch Control:
0:
Disable Prefetch (Must be 0 for CDROM accesses).
1:
Enable Prefetch
Reserved
Post Write Length Control:
The value programmed into this register+1 will be the length of the Post Write Bursts that the
IDE write state machine will attempt to the IDE drive when the AT bus grant is received.
Reserved
Prefetch Length Control:
The value programmed into this register+1 will be the length of the Prefetch Bursts that the
IDE read state machine will attempt to the IDE drive when the AT bus grant is received.
Default
00000000000
000
0
0
00
0
00
0
0
0
00
00
00
00
Note: Register Indices 44H-47H will return all zeroes when read.
Register 13: Primary IDE Address Setup Control Register (Read/Write) − Index=48H with a 32-bit access
Bit
Function
Default
31:8
Reserved
000000H
7:4
Slave Drive IDE Address Set-up Time:
0011
The value programmed into this register +1 will be the setup (in PCI Clock cycles) from
address valid to IOR or IOW valid.
3:0
Master Drive IDE Address Set-up Time:
0011
The value programmed into this register +1 will be the setup (in PCI Clock cycles) from
address valid to IOR or IOW valid.
Register 14: Primary Master Drive IDE IOR Command Control Register (Read/Write) − Index=4CH with an 8-bit access
Bit
Function
Default
7:4
16-Bit Master Drive IDE IOR Command Pulse Width Time:
0011
The value programmed into this register +1 will be the duration (in AT Clock cycles) of the
asserted IOR signal.
3:0
16-Bit Master Drive IDE IOR Command Recovery Time:
0011
The value programmed into this register +1 will be the duration (in AT Clock cycles) that IOR
must be deasserted between transfers.
125