BCM43455 Datasheet, PDF (86/159 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM43455 Preliminary Data Sheet
Pin Descriptions
Pin Descriptions
The signal name, type, and description of each pin in the BCM43455 is listed in Table 19. The symbols shown
under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down
characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
Table 19: Signal Descriptions
Signal Name
WLBGA Ball
WLAN and Bluetooth Receive RF Signal Interface
WRF_RFIN_2G
N8
WRF_RFIN_5G
L11
WRF_PAOUT_2G
N9
WRF_PAOUT_5G
M11
WRF_EXT_TSSIA
K8
WRF_GPAIO_OUT
L8
RF Switch Control Lines
RF_SW_CTRL_0
F11
RF_SW_CTRL_1
F10
RF_SW_CTRL_2
G9
RF_SW_CTRL_3
G8
RF_SW_CTRL_4
F7
RF_SW_CTRL_5
G7
RF_SW_CTRL_6
G6
RF_SW_CTRL_7
F6
RF_SW_CTRL_8
E6
WLAN PCI Express Interface
PCIE_CLKREQ_L
B8
PERST_L
D8
PCIE_RDN
A9
PCIE_RDP
A8
PCIE_REFCLKN
C11
PCIE_REFCLKP
B11
PCIE_TDN
A10
PCIE_TDP
B10
Type Description
I
2.4 GHz Bluetooth and WLAN receiver
shared input.
I
5 GHz WLAN receiver input.
O
2.4 GHz WLAN PA output.
O
5 GHz WLAN PA output.
I
5 GHz TSSI input from an optional
external power amplifier/power detector.
I/O
GPIO or 2.4 GHz TSSI input from an
optional external power amplifier/power
detector.
O
Programmable RF switch control lines.
O
O
The control lines are programmable via
the driver and NVRAM file.
O
O
O
O
O
O
OD
I (PU)
I
I
I
I
O
O
PCIe clock request signal which
indicates when the REFCLK to the PCIe
interface can be gated.
1 = the clock can be gated.
0 = the clock is required.
PCIe System Reset. This input is the
PCIe reset as defined in the PCIe Base
Specification Version 1.1.
Receiver differential pair (×1 lane).
PCIe differential clock inputs (negative
and positive), 100 MHz differential.
Transmitter differential pair (×1 lane).
Broadcom^®
November 5, 2015 • 43455-DS109-R
BROADCOM CONFIDENTIAL
Page 85