BCM43455 Datasheet, PDF (53/159 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM43455 Preliminary Data Sheet
PCM Interface
Long Frame Sync, Master Mode
Figure 13: PCM Timing Diagram (Long Frame Sync, Master Mode)
PCM_BCLK
PCM_SYNC
PCM_OUT
5
PCM_IN
1
4
Bit 0
Bit 0
Bit 1
Bit 1
2
3
8
HIGH IMPEDANCE
6
7
Table 8: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Reference Characteristics
1
PCM bit clock frequency
2
PCM bit clock LOW
3
PCM bit clock HIGH
4
PCM_SYNC delay
5
PCM_OUT delay
6
PCM_IN setup
7
PCM_IN hold
8
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
Minimum
–
41
41
0
0
8
8
0
Typical
–
–
–
–
–
–
–
–
Maximum Unit
12
MHz
–
ns
–
ns
25
ns
25
ns
–
ns
–
ns
25
ns
Broadcom^®
November 5, 2015 • 43455-DS109-R
BROADCOM CONFIDENTIAL
Page 52