BCM43455 Datasheet, PDF (68/159 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM43455 Preliminary Data Sheet
UART Interface
UART Interface
A high-speed 4-wire CTS/RTS UART interface can be enabled by software as an alternate function on GPIO
pins. Provided primarily for debugging during development, this UART enables the BCM43455 to operate as
RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is
compatible with the industry standard 16550 UART, and provides a FIFO size of 64 × 8 in each direction.
JTAG/SWD Interface
The BCM43455 supports IEEE 1149.1 JTAG boundary scan and reduced pin-count Serial Wire Debug (SWD)
mode to access the chip’s internal blocks and backplane for system bring-up and debugging. This interface
allows Broadcom engineers to assist customers with proprietary debug and characterization test tools. It is
highly recommended that customers provide access to at least the SWD pins on all PCB designs by using either
test points or a header.
The SWD interface uses two of the JTAG signals: TMS for bidirectional data (SWDIO) and TCK for the clock
(SWCLK). The debug access port (DAP) embedded in the ARM processor supports both SWD and JTAG
interfaces and can be switched from one to the other through a specific sequence on the TMS/SWD lines. In
addition to the ARM debug interface, an internal JTAG master on the DAP allows access to test access points
(TAPs) in the BCM43455 for hardware debugging.
Broadcom^®
November 5, 2015 • 43455-DS109-R
BROADCOM CONFIDENTIAL
Page 67