CY8C54LP Datasheet, PDF (81/117 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5LP: CY8C54LP Family
Datasheet
Table 11-21. SAR ADC DC Specifications (continued)
Parameter
Description
INL
Integral non linearity^[37]
DNL
Differential non linearity^[37]
R_IN
Input resistance^[37]
Conditions
Min
V_DDA 1.71 to 5.5 V, 1 Msps, V_REF 1 –
to 5.5 V
V_DDA 2.0 to 3.6 V, 1 Msps, V_REF 2
–
to V_DDA
V_DDA 1.71 to 5.5 V, 500 ksps, V_REF –
1 to 5.5 V
V_DDA 1.71 to 5.5 V, 1 Msps, V_REF 1 –
to 5.5 V
V_DDA 2.0 to 3.6 V, 1 Msps, V_REF 2
–
to V_DDA
No missing codes
V_DDA 1.71 to 5.5 V, 500 ksps, V_REF –
1 to 5.5 V
No missing codes
–
Typ
Max
–
+2/–1.5
Units
LSB
–
±1.2
LSB
–
±1.3
LSB
–
+2/–1
LSB
– 1.7/–0.99 LSB
– +2/–0.99 LSB
180
–
kΩv
Figure 11-29. SAR ADC DNL vs Output Code,
Bypassed Internal Reference Mode
Figure 11-30. SAR ADC I_DD vs sps, V_DDA = 5 V, Continuous
Sample Mode, External Reference Mode
Figure 11-31. SAR ADC INL vs Output Code,
Bypassed Internal Reference Mode
Note
37. Based on device characterization (Not production tested).
Document Number: 001-84934 Rev. **
Page 81 of 117