CY8C54LP Datasheet, PDF (33/117 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5LP: CY8C54LP Family
Datasheet
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in Table 6-6. Three configuration bits
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers. Figure 6-11 depicts a simplified pin view based on
each of the eight drive modes. Table 6-6 shows the I/O pin’s drive
state based on the port data register value or digital array signal
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull-up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
Vddio
Vddio
DR
PS
Pin
DR
PS
Pin
DR
PS
Pin
DR
PS
Pin
0. High Impedance 1. High Impedance 2. Resistive
Analog
Digital
Pull-Up
Vddio
Vddio
3. Resistive
Pull-Down
Vddio
DR
PS
Pin
DR
PS
Pin
DR
PS
Pin
DR
PS
Pin
4. Open Drain,
Drives Low
5. Open Drain,
Drives High
6. Strong Drive
7. Resistive
Pull-Up and Pull-Down
Table 6-6. Drive Modes
Diagram
0
1
2
3
4
5
6
7
Drive Mode
High impedence analog
High Impedance digital
Resistive pull-up^[9]
Resistive pull-down^[9]
Open drain, drives low
Open drain, drive high
Strong drive
Resistive pull-up and pull-down^[9]
PRTxDM2
0
0
0
0
1
1
1
1
PRTxDM1
0
0
1
1
0
0
1
1
PRTxDM0
0
1
0
1
0
1
0
1
PRTxDR = 1
High-Z
High-Z
Res High (5K)
Strong High
High-Z
Strong High
Strong High
Res High (5K)
PRTxDR = 0
High-Z
High-Z
Strong Low
Res Low (5K)
Strong Low
High-Z
Strong Low
Res Low (5K)
Note
9. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Document Number: 001-84934 Rev. **
Page 33 of 117