CY8C54LP Datasheet, PDF (75/117 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5LP: CY8C54LP Family
Datasheet
Figure 11-16. USBIO Output High Voltage and Current, GPIO
Mode
Figure 11-17. USBIO Output Low Voltage and Current, GPIO
Mode
Table 11-14. USBIO AC Specifications
Parameter
Description
Tdrate
Full-speed data rate average bit rate
Conditions
Tjr1
Tjr2
Tdj1
Tdj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Fgpio_out
Tr_gpio
Tf_gpio
Receiver data jitter tolerance to next
transition
Receiver data jitter tolerance to pair
transition
Driver differential jitter to next transition
Driver differential jitter to pair transition
Source jitter for differential transition to
SE0 transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential
transition
GPIO mode output operating frequency 3 V ≤ V_DDD ≤ 5.5 V
V_DDD = 1.71 V
Rise time, GPIO mode, 10%/90% V_DDD V_DDD > 3 V, 25 pF load
V_DDD = 1.71 V, 25 pF load
Fall time, GPIO mode, 90%/10% V_DDD V_DDD > 3 V, 25 pF load
V_DDD = 1.71 V, 25 pF load
Min
Typ
12 – 0.25% 12
–8
–
–5
–
–3.5
–
–4
–
–2
–
160
–
82
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
12 +
0.25%
8
Units
MHz
ns
5
ns
3.5
ns
4
ns
5
ns
175
ns
–
ns
14
ns
20
MHz
6
MHz
12
ns
40
ns
12
ns
40
ns
Document Number: 001-84934 Rev. **
Page 75 of 117