W320-03_05 Datasheet, PDF (8/18 Pages) Cypress Semiconductor – 200-MHz Spread Spectrum Clock Synthesizer/Driver

W320-03
Switching Characteristics^[10] Over the Operating Range
Parameter
Output
Description
t₁
All
Output Duty Cycle^[11]
t₃
USB, REF, DOT Falling Edge Rate
t₃
PCI,3V66
Falling Edge Rate
t₅
3V66[0:1]
3V66-3V66 Skew
t₅
66BUFF[0:2] 66BUFF-66BUFF Skew
t₆
PCI
PCI-PCI Skew
t₇
3V66,PCI
3V66-PCI Clock Jitter
t₉
3V66
Cycle-Cycle Clock Jitter
t₉
USB, DOT
Cycle-Cycle Clock Jitter
t₉
PCI
Cycle-Cycle Clock Jitter
t₉
REF
Cycle-Cycle Clock Jitter
CPU 1.0V Switching Characteristics
Test Conditions
Measured at 1.5V
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at 1.5V
Measured at 1.5V
Measured at 1.5V
3V66 leads. Measured at 1.5V
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
t₂
CPU
RiseTime
Measured differential waveform from
–0.35V to +0.35V
t₃
CPU
Fall Time
Measured differential waveform from
–0.35V to +0.35V
t₄
CPU
CPU-CPU Skew
t₈
CPU
Cycle-Cycle Clock Jitter
CPU
Rise/Fall Matching
V_oh
CPU
High-level Output Voltage
including overshoot
V_ol
CPU
Low-level Output Voltage
including undershoot
V_crossover
CPU
Crossover Voltage
CPU 0.7V Switching Characteristics
Measured at Crossover
Measured at Crossover t₈ = t_8A – t_8B
Measured with test loads^[12]
Measured with test loads^[12]
Measured with test loads^[12]
Measured with test loads^[12]
t₂
CPU
RiseTime
Measured single ended waveform from
0.175V to 0.525V
t₃
CPU
Fall Time
Measured single ended waveform from
0.175V to 0.525V
t₄
CPU
CPU-CPU Skew
Measured at Crossover
t₈
CPU
Cycle-Cycle Clock Jitter Measured at Crossover t₈ = t_8A – t_8B
With all outputs running
CPU
Rise/Fall Matching
Measured with test loads^{[13, 14]}
V_oh
CPU
High-level Output Voltage Measured with test loads^[14]
including overshoot
V_ol
CPU
Low-level Output Voltage Measured with test loads^[14]
including undershoot
V_crossover
CPU
Crossover Voltage
Measured with test loads^[14]
Notes:
10. All parameters specified with loaded outputs.
11. Duty cycle is measured at 1.5V when V_DD = 3.3V. When V_DD = 2.5V, duty cycle is measured at 1.25V.
12. The 1.0V test load is shown on test circuit page.
13. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.
14. The 0.7V test load is R_s = 33.2Ω, R_p = 49.9Ω in test circuit.
Min.
45
0.5
1.0
1.5
175
175
0.92
–0.2
0.51
175
175
–0.15
0.28
Max.
55
2.0
4.0
500
175
500
3.5
250
350
500
1000
467
467
150
150
325
1.45
0.35
0.76
700
700
150
150
20
0.85
0.43
Unit
%
ps
V/ns
ps
ps
ps
ns
ps
ps
ps
ps
ps
ps
ps
ps
mV
V
V
V
ps
ps
ps
ps
%
V
V
V
Document #: 38-07248 Rev. *C
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