W320-03_05 Datasheet, PDF (3/18 Pages) Cypress Semiconductor – 200-MHz Spread Spectrum Clock Synthesizer/Driver

W320-03
Function Table ^[1]
S2 S1 S0
1 00
1 01
1 10
1 11
0 00
0 01
0 10
0 11
Mid 0 0
Mid 0 1
Mid 1 0
Mid 1 1
CPU
(MHz)
66 MHz
100 MHz
200 MHz
133 MHz
66 MHz
100 MHz
200 MHz
133 MHz
Hi-Z
TCLK/2
Reserved
Reserved
3V66[0:1] 66BUFF[0:2]/3 66IN/3V66_5 PCI_F/PCI
(MHz) V66[2:4] (MHz) (MHz)
(MHz)
66 MHz 66 IN
66 MHz Input 66 IN/2
66 MHz 66 IN
66 MHz Input 66 IN/2
66 MHz 66 IN
66 MHz Input 66 IN/2
66 MHz 66 IN
66 MHz Input 66 IN/2
66 MHz 66 MHz
66 MHz
33 MHz
66 MHz 66 MHz
66 MHz
33 MHz
66 MHz 66 MHz
66 MHz
33 MHz
66 MHz 66 MHz
66 MHz
33 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TCLK/4 TCLK/4
TCLK/4
TCLK/8
Reserved Reserved
Reserved
Reserved
Reserved Reserved
Reserved
Reserved
USB/DOT
REF0(MHz) (MHz)
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
Hi-Z
Hi-Z
TCLK
TCLK/2
Reserved Reserved
Reserved Reserved
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
6, 7, 8
–
–
Swing Select Functions
Mult0
0
Board Target
Trace/Term Z
60Ω
1
50Ω
Reference R, IREF ₌
V_DD/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Output
Current
I_OH = 4*IREF
I_OH = 6*IREF
V_OH @ Z
1.0V @ 50
0.7V @ 50
Clock Driver Impedances
Buffer Name
CPU, CPU#
REF
PCI, 3V66, 66BUFF
USB
DOT
V_DD Range
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
Buffer Type
Type X1
Type 3
Type 5
Type 3A
Type 3B
Minimum
Ω
20
12
12
12
Impedance
Typical
Ω
50
40
30
30
30
Maximum
Ω
60
55
55
55
Clock Enable Configuration
VCOS/
PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT OSC
0
X
X
IREF*2 FLOAT LOW LOW LOW LOW LOW
OFF
1
0
0
IREF*2 FLOAT ON
ON
ON OFF
ON
ON
1
0
1
IREF*2 FLOAT ON
ON
ON ON
ON
ON
1
1
0
ON
ON ON
ON
ON OFF
ON
ON
1
1
1
ON
ON ON
ON
ON ON
ON
ON
Notes:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation.
3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.
6. TCLK is a test clock over driven on the XTAL_IN input during test mode.
7. Required for DC output impedance verification.
8. These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
Document #: 38-07248 Rev. *C
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