W209C Datasheet, PDF (8/16 Pages) SpectraLinear Inc – Frequency Generator for Integrated Core Logic with 133MHz FSB

PRELIMINARY
W209C
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Bit 7
31
DCLK
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
47
APIC
Bit 2
-
Reserved
Bit 1
-
Reserved
Bit 0
-
Reserved
Default
1
0
0
0
1
0
1
0
(Active/Inactive)
Reserved
Reserved
Reserved
(Active/Inactive)
Reserved
Reserved
Reserved
Pin Description
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Bit 7
-
SEL3
0
Bit 6
-
SEL2
0
Bit 5
-
SEL1
0
Bit 4
-
SEL0
0
Bit 3
-
FS(0:4) Override
0
Bit 2
-
SEL4
0
Bit 1
-
Reserved
1
Bit 0
-
Test Mode
0
Pin Function
See Table 4
See Table 4
See Table 4
See Table 4
0 = Select operating frequency by FS(0:4) strapping
1 = Select operating frequency by SEL(0:4) bit settings
See Table 4
Reserved
0 = Normal
1 = Three-stated
Byte 5: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Bit 7
-
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
Reserved
Bit 1
-
Reserved
Bit 0
-
Reserved
Default
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin Description
Byte 6: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Bit 7
-
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
Reserved
Bit 1
-
Reserved
Bit 0
-
Reserved
Default
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin Description
Document #: 38-07171 Rev. *A
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