W209C Datasheet, PDF (12/16 Pages) SpectraLinear Inc – Frequency Generator for Integrated Core Logic with 133MHz FSB

PRELIMINARY
W209C
AC Electrical Characteristics^[9]
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, V_DDQ2= 2.5V±5%
f_XTL = 14.31818 MHz
66.6-MHz Host
Parameter
Description
Min. Max.
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
Host/CPUCLK Period
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
15.0 15.5
5.2
N/A
5.0
N/A
0.4
1.6
0.4
1.6
100-MHz Host
Min. Max.
10.0 10.5
3.0
N/A
2.8
N/A
0.4
1.6
0.4
1.6
133-MHz Host
Min.
Max.
7.5
8.0
1.87
N/A
1.67
N/A
0.4
1.6
0.4
1.6
Unit Notes
ns 11
ns 14
ns 15
ns
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
SDRAM CLK Period
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
10.0 10.5 10.0 10.5 10.0
10.5
ns 11
3.0
N/A
3.0
N/A
3.0
N/A
ns 14
2.8
N/A
2.8
N/A
2.8
N/A
ns 15
0.4
1.6
0.4
1.6
0.4
1.6
ns
0.4
1.6
0.4
1.6
0.4
1.6
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
APIC 33-MHz CLK Period
APIC 33-MHz CLK High Time
APIC 33-MHz CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
30.0 N/A 30.0 N/A
30.0
12.0 N/A 12.0 N/A
12.0
12.0 N/A 12.0 N/A
12.0
0.4
1.6
0.4
1.6
0.4
0.4
1.6
0.4
1.6
0.4
N/A
ns 11
N/A
ns 14
N/A
ns 15
1.6
ns
1.6
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
3V66 CLK Period
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
15.0 16.0 15.0 16.0 15.0
16.0
ns 11, 13
5.25 N/A 5.25 N/A
5.25
N/A
ns 14
5.05 N/A 5.05 N/A
5.05
N/A
ns 15
0.5
2.0
0.5
2.0
0.5
2.0
ns
0.5
2.0
0.5
2.0
0.5
2.0
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
PCI CLK Period
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
30.0 N/A 30.0 N/A
30.0
12.0 N/A 12.0 N/A
12.0
12.0 N/A 12.0 N/A
12.0
0.5
2.0
0.5
2.0
0.5
0.5
2.0
0.5
2.0
0.5
N/A
ns 11, 12
N/A
ns 14
N/A
ns 15
2.0
ns
2.0
ns
tp_ZL, tp_ZH Output Enable Delay (All outputs) 1.0
10.0
1.0
10.0
1.0
tp_LZ, tp_ZH Output Disable Delay
(All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
10.0
ns
t_stable
All Clock Stabilization from
Power-Up
3
3
3
ms
Notes:
11. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
12. T_HIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
13. T_LOW is measured at 0.4V for all outputs.
14. The time specified is measured from when V_DDQ3 achieves its nominal operating level (typical condition V_DDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
15. T_RISE and T_FALL are measured as a transition through the threshold region V_ol = 0.4V and V_oh = 2.0V (1 mA) JEDEC specification.
Document #: 38-07171 Rev. *A
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