W209C Datasheet, PDF (7/16 Pages) SpectraLinear Inc – Frequency Generator for Integrated Core Logic with 133MHz FSB

PRELIMINARY
W209C
W209C Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0 = Disable)^[8]
Bit
Pin#
Name
Bit 7
-
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
23
24/48 MHz
Bit 1
21, 22
48 MHz
Bit 0
-
Reserved
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current. The controller will read
back the written value.
Default
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
(Active/Inactive)
(Active/Inactive)
Reserved
Pin Function
Byte 1: Control Register (1 = Enable, 0 = Disable)^[8]
Bit
Pin#
Name
Bit 7
32
SDRAM7
Bit 6
33
SDRAM6
Bit 5
35
SDRAM5
Bit 4
36
SDRAM4
Bit 3
37
SDRAM3
Bit 2
39
SDRAM2
Bit 1
40
SDRAM1
Bit 0
41
SDRAM0
Default
1
1
1
1
1
1
1
1
Pin Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable)^[8]
Bit
Pin#
Name
Default
Pin Description
Bit 7
19
PCI7
1
(Active/Inactive)
Bit 6
18
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
15
PCI4
1
(Active/Inactive)
Bit 3
14
PCI3
1
(Active/Inactive)
Bit 2
12
PCI2
1
(Active/Inactive)
Bit 1
11
PCI1
1
(Active/Inactive)
Bit 0
10
PCI0
1
(Active/Inactive)
Note:
8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Document #: 38-07171 Rev. *A
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