STAR1000_11 Datasheet, PDF (8/24 Pages) Cypress Semiconductor – 1M Pixel Radiation Hard CMOS Image Sensor

Architecture
Floor Plan
Reset
Reset_DS
Vref
Ld_Y
A0....A9
1024
Rst
Y Address
Decoder
10
and Logic
1024
Rd
Figure 3. STAR1000 Floor Plan
Pixel Array
1024 x 1024 pixels
Col
Rst
Rd
10
S
R
Clk_X
1024
1024
Column Amplifiers
1024
1024
1024
10
X Register
X Address Decoder
Rst
Progr. Gain
Sig ^Amplifier
STAR1000
10-bit ADC
10
D0...D9
Clk_ADC
Ain
Buffer
Aout
Ld_X
The image sensor contains five sections: the pixel array, the X-
and Y- addressing logic, the column amplifiers, the output
amplifier and the ADC. Figure 3 shows an outline diagram of the
sensor, including an indication of the main control signals. The
following paragraphs explain the function and operation of the
different imager parts in detail.
Pixel Array
The pixel array contains 1024 by 1024 active pixels at 15 μm
pitch. Each pixel contains one photo diode and three transistors
(Figure 4).
The photo diode is always in reverse bias. At the beginning of
the integration cycle, a pulse is applied to the reset line (gate of
T1) bringing the cathode of D1 to the reset voltage level. During
the integration period, photon-generated electrons accumulate
on the diode capacitance reducing the voltage on the gate of T2.
The real illumination dependent signal is the difference between
the reset level and the output level after integration. This
difference is created in the column amplifiers. T2 acts as a
source follower and T3 allows connection of the pixel signal
(reset level and output level) to the vertical output bus.
The reset lines and the read lines of the pixels in a row are
connected together to the Y- decoder logic; the outputs of the
pixels in a column are connected together to a column amplifier.
Figure 4. Architecture of the 3T Pixel
T1
Reset
Read
T2
T3
Document Number: 38-05714 Rev. *F
Page 8 of 24
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