CY8C53_11 Datasheet, PDF (75/106 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 67 MHz operation

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
11.5.5 Comparator
Table 11-24. Comparator DC Specifications
Parameter
V_OS
V_OS
V_OS
V_HYST
V_ICM
CMRR
I_CMP
Description
Conditions
Input offset voltage in fast mode Factory trim, Vin ≥ 0.5 V
Input offset voltage in slow mode Factory trim, Vin ≥ 0.5 V
Input offset voltage in fast mode^[27] Custom trim
Input offset voltage in slow mode^[27] Custom trim
Input offset voltage in ultra low
power mode
Hysteresis
Hysteresis enable mode
Input common mode voltage
High current / fast mode
Low current / slow mode
Ultra low power mode
Common mode rejection ratio
High current mode/fast mode^[28]
Low current mode/slow mode^[28]
Ultra low power mode^[28]
Table 11-25. Comparator AC Specifications
Parameter
T_RESP
Description
Response time, high current
mode^[28]
Response time, low current
mode^[28]
Response time, ultra low power
mode^[28]
Conditions
50 mV overdrive, measured
pin-to-pin
50 mV overdrive, measured
pin-to-pin
50 mV overdrive, measured
pin-to-pin
Min
–
–
–
–
–
–
V_SSA
V_SSA
V_SSA
–
–
–
–
Typ
Max
Units
10
mV
9
mV
–
4
mV
–
4
mV
±12
–
mV
10
32
mV
– V_DDA – 0.1
V
–
V_DDA
V
– V_DDA – 0.9
50
–
dB
–
400
µA
–
100
µA
6
–
µA
Min Typ
Max
–
75
110
–
155
200
–
55
–
Units
ns
ns
µs
Notes
27. The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM.
28. Based on device characterization (Not production tested).
Document Number: 001-66237 Rev. *A
Page 75 of 106
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