CY8C53_11 Datasheet, PDF (48/106 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 67 MHz operation

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C38,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
8.2 Successive Approximation ADC
The CY8C53 family of devices has a Successive Approximation
(SAR) ADC. This ADC is 12-bit at up to 1 Msps, with
single-ended or differential inputs, making it useful for a wide
variety of sampling and control applications.
8.2.1 Functional Description
In a SAR ADC an analog input signal is sampled and compared
with the output of a DAC. A binary search algorithm is applied to
the DAC and used to determine the output bits in succession
from MSB to LSB. A block diagram of one SAR ADC is shown in
Figure 8-3.
Figure 8-3. SAR ADC Block Diagram
vin
vrefp
vrefn
S/H
DAC
array
POWER
GROUND
power
filtering
comparator
autozero
reset
clock
clock
vrefp
vrefn
SAR
digital ^D0:D11
The input is connected to the analog globals and muxes. The
frequency of the clock is 16 times the sample rate; the maximum
clock rate is 16 MHz.
8.2.2 Conversion Signals
Writing a start bit or assertion of a Start of Frame (SOF) signal is
used to start a conversion. SOF can be used in applications
where the sampling period is longer than the conversion time, or
when the ADC needs to be synchronized to other hardware. This
signal is optional and does not need to be connected if the SAR
ADC is running in a continuous mode. A digital clock or UDB
output can be used to drive this input. When the SAR is first
powered up or awakened from any of the sleeping modes, there
is a power up wait time of 10 µs before it is ready to start the first
conversion.
When the conversion is complete, a status bit is set and the
output signal End of Frame (EOF) asserts and remains asserted
until the value is read by either the DMA controller or the CPU.
The EOF signal may be used to trigger an interrupt or a DMA
request.
8.2.3 Operational Modes
A ONE_SHOT control bit is used to set the SAR ADC conversion
mode to either continuous or one conversion per SOF signal.
DMA transfer of continuous samples, without CPU intervention,
is supported.
8.3 Comparators
The CY8C53 family of devices contains four comparators.
Comparators have these features:
„ Input offset factory trimmed to less than 5 mV
„ Rail-to-rail common mode input range (V_SSA to V_CCA)
„ Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
„ Comparator outputs can be routed to look up tables to perform
simple logic functions and then can also be routed to digital
blocks
„ The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
„ Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
8.3.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
Document Number: 001-66237 Rev. *A
Page 48 of 106
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