CY8C53_11 Datasheet, PDF (10/106 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 67 MHz operation

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C53 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard
architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling
features.
Figure 4-1. ARM Cortex-M3 Block Diagram
Interrupt Inputs
Nested
Vectored
Interrupt
Controller
(NVIC)
Flash Patch and
Breakpoint
(FPB)
Cortex M3 CPU Core
SWD
Debug Block
(SWD)
I- Bus D- Bus
S-Bus
32 KB
SRAM
Bus
Matrix
C- Bus
Cortex M3 Wrapper
AHB
AHB
Bus
Matrix
Data
Watchpoint and
Trace (DWT)
Instrumentation
Trace Module
(ITM)
Trace Port
Interface Unit
(TPIU)
SWV
Cache
256 KB
Flash
32 KB
SRAM
Bus
Matrix
AHB Spokes
AHB
AHB Bridge and Bus Matrix
PHUB
DMA
GPIO
Prog.
Digital
Prog.
Analog
Special
Functions
Peripherals
The Cortex-M3 CPU subsystem includes these features:
„ ARM Cortex-M3 CPU
„ Programmable NVIC, tightly integrated with the CPU core
„ Full-featured debug and trace module, tightly integrated with
the CPU core
„ Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB
of SRAM
„ Cache controller
„ Peripheral HUB (PHUB)
„ DMA controller
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
„ 4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
„ The Thumb^®-2 instruction set, which offers ARM-level
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
‡ Bit-field control
‡ Hardware multiply and divide
‡ Saturation
‡ If-Then
‡ Wait for events and interrupts
‡ Exclusive access and barrier
‡ Special register access
The Cortex-M3 does not support ARM instructions.
Document Number: 001-66237 Rev. *A
Page 10 of 106
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