CY8C53_11 Datasheet, PDF (60/106 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 67 MHz operation

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
Table 11-3. AC Specifications^[14]
Parameter
Description
Conditions
Min
F_CPU
CPU frequency
DC
F_BUSCLK Bus frequency
DC
Svdd
V_DD ramp rate
–
T_{IO_INIT}
Time from V_DDD/V_DDA/V_CCD/V_CCA
–
≥ IPOR to I/O ports set to their reset
states
T_STARTUP Time from V_DDD/V_DDA/V_CCD/V_CCA No PLL used, IMO boot mode 12 MHz
–
≥ min operating voltage to CPU typ.
executing code at reset vector
T_SLEEP
Wakeup from limited active mode –
–
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
T_HIBERNATE Wakeup form hibernate mode –
–
Application of external interrupt to
beginning of execution of next CPU
instruction
Typ
Max Units
–
67.01 MHz
–
67.01 MHz
–
1
V/ns
–
10
µs
–
66
µs
20
–
µs
–
100
µs
Note
14. Based on device characterization (Not production tested).
Document Number: 001-66237 Rev. *A
Page 60 of 106
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