W137 Datasheet, PDF (7/10 Pages) Cypress Semiconductor – Bx Notebook System Frequency Synthesizer

W137
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock
Covers all CPU/PCI outputs. Measured on rising
Offset
edge at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabiliza- Assumes full supply voltage reached within 1 ms
tion from Power-up
from power-up. Short cycles exist prior to frequency
(cold start)
stabilization.
Z_o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
30
12.0
12.0
1
4
1
4
45
55
250
500
1.5
4.0
3
20
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
t_R
t_F
t_D
f_ST
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
Z_o
AC Output Impedance
Test Condition/Comments
Determined by crystal oscillator frequency
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
14.318
0.5
2
0.5
2
45
55
3
25
Unit
MHz
V/ns
V/ns
%
ms
Ω
7