W137 Datasheet, PDF (2/10 Pages) Cypress Semiconductor – Bx Notebook System Frequency Synthesizer

W137
Pin Definitions
Pin Name
CPU0:1
Pin
No.
24, 23
PCI1:5
PCI_F
5, 6, 9, 10,
11
4
CPU_STOP#
18
PCI_STOP#
20
REF0/SEL48#
27
REF1/SPREAD#
26
24/48MHz/OE
14
48MHz
13
SEL100/66#
16
X1
2
X2
3
PWR_DWN#
17
VDDQ3
VDDQ2
GND
8, 12, 19, 28
25
1, 7, 15, 21,
22
Pin
Type
O
O
O
I
I
I/O
I/O
I/O
O
I
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2. Frequency is selected per Table 1.
PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3. Frequency is selected per Table 1.
Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1.
CPU_STOP# Input: When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency).
PCI_STOP# Input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
I/O Dual-Function REF0 and SEL48# Pin: Upon power-up, the state of SEL48# is
latched. The state is set by either a 10K resistor to GND or to V_DD. A 10K resistor to
GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to V_DD, pin 14
will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that
produces a copy of 14.318 MHz.
I/O Dual-Function REF1 and SPREAD# Pin: Upon power-up, the state of
SPREAD# is latched. The state is set by either a 10K resistor to GND or to V_DD. A
10K resistor to GND enables Spread Spectrum function. If the pin is strapped to V_DD,
Spread Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that
produces a copy of 14.318 MHz.
I/O Dual-Function 24-MHz or 48-MHz Output and Output Enable Input: Upon
power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to
GND or to V_DD. A 10K resistor to GND latches OE LOW, and all outputs are three-
stated. If the pin is strapped to V_DD, OE is latched HIGH and all outputs are active.
After 2 ms, the pin becomes an output whose frequency is set by the state of pin 27
on power-up.
48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
Frequency Selection Input: Select power-up default CPU clock frequency as shown
in Table 1.
Crystal Connection or External Reference Frequency Input: This pin can either
be used as a connection to a crystal or to a reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control: When this input is LOW, device goes into a low-power standby
condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (2–3 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
Power Connection: Connected to 3.3V.
Power Connection: Power supply for CPU0:1 output buffers. Connected to 2.5V.
Ground Connection: Connect all ground pins to the common system ground plane.
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