MB3773 Datasheet, PDF (7/31 Pages) Fujitsu Component Limited. – Power Supply Monitor with Watch-Dog Timer

MB3773
4. Operation Sequence
1. When Vcc rises to about 0.8 V, RESET goes “Low” and RESET goes “High”.
The pull-up current of approximately 1 μA (Vcc = 0.8 V) is output from RESET.
2. When Vcc rises to V_SH ( =: 4.3V) , the charge with C_T starts.
At this time, the output is being reset.
3. When C_T begins charging, RESET goes “High” and RESET goes “Low”.
After T_PR reset of the output is released.
Reset hold time: T_PR (ms) =: 1000 × C_T (μF)
After releasing reset, the discharge of C_T starts, and watch-dog timer operation starts.
T_PR is not influenced by the CK input.
4. C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal while discharging C_T.
5. C changes from the charge into the discharge when the voltage of C_T reaches a constant
threshold ( =: 1.4 V) .
4 and 5 are repeated while a normal clock is input by the logic system.
6. When the clock is cut off, gets, and the voltage of C_T falls on threshold (=: 0.4 V) of reset on, RESET goes “Low” and RESET goes
“High”.
Discharge time of C_T until reset is output: T_WD is watch-dog timer monitoring time.
T_WD (ms) =: 100 × C_T (μF)
Because the charging time of
T_WD becomes maximum T_WD
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7. Reset time in operating watch-dog timer: T_WR is charging time where the voltage of C_T goes up to off
threshold ( =: 1.4 V) for reset.
T_WR (ms) =: 20 × C_T (μF)
Reset of the output is released after C_T reaches an off threshold for reset, and C_T starts the discharge, after that if the clock is
normally input, operation repeats 4 and 5, when the clock is cut off, operationrepeats 6 and 7.
8. When Vcc falls on V_SL ( =: 4.2 V) , reset is output. C_T is rapidly discharged of at the same time.
9. When Vcc goes up to V_SH, the charge with C_T is started.
When Vcc is momentarily low,
After falling V_SL or less Vcc, the time to going up is the standard value of the Vcc input pulse width in V_SH or more.
After the charge of C_T is discharged, the charge is started if it is T_PI or more.
10.Reset of the output is released after T_PR, after Vcc becomes V_SH or more, and the watch-dog timer starts. After that, when Vcc
becomes V_SL or less, 8 to 10 is repeated.
11.While power supply is off, when Vcc becomes V_SL or less, reset is output.
12.The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.
Document Number: 002-08513 Rev. *A
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