MB3773 Datasheet, PDF (25/31 Pages) Fujitsu Component Limited. – Power Supply Monitor with Watch-Dog Timer

MB3773
EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency
V_CC (5 V)
R₂
1
8
RESET
2
7
C_T
3
6
4
5
R₁=10 kΩ
RESET
CK
T_r1
C₂
GND
Notes :
• This is an example application to limit upper frequency fH of clock pulses sent from the microprocessor.
If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal.
(The lower frequency has already been set using C_T.)
• When a clock pulse such as shown below is sent to terminal CK, a short T₂ prevents C₂ voltage from reaching the
CK input threshold level ( =: 1.25 V), and will cause a reset signal to be output.
The T₁ value can be found using the following formula :
T₁=: 0.3 C₂R₂
where V_CC  5 V, T₃  3.0 μs, T₂  20 μs
T₂
CK waveform
T₃
C₂ voltage
T
Example : Setting C and R allow the upper T₁ value to be set (Refer to the table below).
C
R
T1
0.01 μF
10 kΩ
30μs
0.1 μF
10 kΩ
300 μs
Document Number: 002-08513 Rev. *A
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