CYD04S72V_11 Datasheet, PDF (7/30 Pages) Cypress Semiconductor – FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM

CYD04S72V
CYD09S72V
CYD18S72V
Master Reset
The FLEx72 family devices undergo a complete reset by taking
the MRST input LOW. MRST input can switch asynchronously to
the clocks. MRST initializes the internal burst counters to zero,
and the counter mask registers to all ones (completely
unmasked). MRST also forces the mailbox interrupt (INT) flags
and the Counter Interrupt (CNTINT) flags HIGH. MRST must be
performed on the FLEx72 family devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports using 18 Mbit device
as an example. The highest memory location, 3FFFF is the
mailbox for the right port and 3FFFE is the mailbox for the left
port. Table 2.shows that in order to set the INT_R flag, a write
Table 2. Interrupt Operation Example ^{[22, 23, 24, 25]}
Function
Set Right INT_R Flag
Reset Right INT_R Flag
Set Left INT_L Flag
Reset Left INT_L Flag
R/W_L
L
X
X
H
Left Port
CE_L
L
A_0L–17L
3FFFF
X
X
X
X
L
3FFFE
operation by the left port to address 3FFFF will assert INT_R LOW.
At least one byte has to be active for a write to generate an
interrupt. A valid Read of the 3FFFF location by the right port will
reset INT_R HIGH. At least one byte has to be active in order for
a read to reset the interrupt. When one port writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to is
asserted LOW.
The INT is reset when the owner (port) of the mailbox reads the
contents of the mailbox. The interrupt flag is set in a flow-thru
mode (i.e., it follows the clock edge of the writing port). Also, the
flag is reset in a flow-thru mode (i.e., it follows the clock edge of
the reading port)
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
INT_L
X
X
L
H
R/W_R
X
H
L
X
Right Port
CE_R
X
A_0R–17R
X
L
3FFFF
L
3FFFE
X
X
INT_R
L
H
X
X
Notes
22. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
23.
CE is internal signal. CE = LOW if
can be deasserted after that. Data
CwEill_{0b=eLoOuWt afatenrdtCheE1fo=lloHwIGinHg.CFLoKr}
a single Read operation, CE only needs to be asserted
edge and will be three-stated after the next CLK edge.
once
at
the
rising
edge
of
the
CLK
and
24. OE is “Don’t Care” for mailbox operation.
25. At least one of BE0 or BE7 must be LOW.
Document Number : 38-06069 Rev. *L
Page 7 of 30
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