CYD04S72V_11 Datasheet, PDF (24/30 Pages) Cypress Semiconductor – FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM

CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 14. Counter Interrupt and Retransmit^{[68, 69, 70, 71, 72]}
CLK
t_CYC2
t_CH2
t_CL2
t_SCM
t_HCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
CNTINT
CLK_L
L_PORT
ADDRESS
INT_R
CLK_R
1FFFC
1FFFD
1FFFE
t_SCINT
1FFFF
t_RCINT
Last_Loaded
Last_Loaded +1
t_CYC2
t_CH2
t_CL2
Figure 15. Mailbox Interrupt Timing^{[73, 74, 75, 76, 77]}
t_SA t_HA
3FFFF
A_n
t_SINT
t_CYC2
t_CH2
t_CL2
A_n+1
t_RINT
A_n+2
A_n+3
R_PORT
ADDRESS
t_SA t_HA
A_m
A_m+1
3FFFF
A_m+3
Notes
68. CE₀ = OE = BE0 – BE7 = LOW; CE₁ = R/W = CNTRST = MRST = HIGH.
69. CNTINT is always driven.
70. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
71. The mask register assumed to have the value of 1FFFFh.
72. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
73. CE₀ = OE = ADS = CNTEN = LOW; CE₁ = CNTRST = MRST = CNT/MSK = HIGH.
74. Address “1FFFF” is the mailbox location for R_Port.
75. L_Port is configured for Write operation, and R_Port is configured for Read operation.
76. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
77. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
A_m+4
Document Number : 38-06069 Rev. *L
Page 24 of 30
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