CYD04S72V_11 Datasheet, PDF (17/30 Pages) Cypress Semiconductor – FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM

CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
MRST
ALL
t_RSF
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
t_RS
t_{RSS tRSR}
INACTIVE
Figure 4. Master Reset
ACTIVE
INT
TDO
CLK
Figure 5. Read Cycle^{[43, 44, 45, 46, 47]}
t_CH2
t_CYC2
t_CL2
CE
t_SC
t_HC
t_SB
t_HB
BE0–BE7
t_SC
t_HC
R/W
ADDRESS
DATA_OUT
t_SW
t_SA
A_n
t_HW
t_HA
1 Latency
A_n+1
t_CD2
t_CKLZ
OE
A_n+2
Q_n
A_n+3
t_DC
Q_n+1
t_OHZ
t_OLZ
t_OE
Q_n+2
Notes
43.
CE is internal signal. CE = LOW if
can be deasserted after that. Data
CwEill_{0b=eLoOuWt afatenrdtCheE1fo=lloHwIGinHg.CFLoKr}
a single Read
edge and will
operation, CE only needs to be asserted
be three-stated after the next CLK edge.
once
at
the
rising
edge
of
the
CLK
and
44. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
45. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
46. The output is disabled (high-impedance state) by CE = V_IH following the next rising edge of the clock.
47.
Addresses do not have to be accessed
Numbers are for reference only.
sequentially
since
ADS
=
CNTEN
=
V_IL
with
CNT/MSK
=
V_IH
constantly
loads
the
address
on
the
rising
edge
of
the
CLK.
Document Number : 38-06069 Rev. *L
Page 17 of 30
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