CYD04S72V_11 Datasheet, PDF (12/30 Pages) Cypress Semiconductor – FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM

CYD04S72V
CYD09S72V
CYD18S72V
18 Mbit
TDO
D2
TDI
Figure 3. Scan Chain
TDO
D4
TDI
TDO
4 Mbit/9 Mbit
TDO
D2
TDI
TDO
TDO
D1
TDI
TDO
D3
TDI
TDO
D1
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Revision number(31:28)
Cypress device(27:12)
Cypress JDEC ID(11:1)
ID register presence (0)
Value
0h
C002h
C001h
034h
1
TDI
Description
Reserved for version number
Defines Cypress DIE number for CYD18S72V and
CYD09S72V
Defines Cypress DIE number for CYD04S72V
Allows unique identification of FLEx72 family device vendor
Indicates the presence of an ID register
Table 5. Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary scan
Bit Size
4
1
32
n^[34]
Table 6. Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
NBSRST
RESERVED
Code
0000
1111
1011
0111
0100
1000
1100
All other codes
Description
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO
Places the BYR between TDI and TDO
Loads the IDR with the vendor ID code and places the register between TDI and TDO
Places BYR between TDI and TDO. Forces all FLEx72 output drivers to a High-Z state
Controls boundary to 1/0. Places BYR between TDI and TDO
Captures the input/output ring contents. Places BSR between TDI and TDO
Resets the non-boundary scan logic. Places BYR between TDI and TDO
Other combinations are reserved. Do not use other than the above
Note
34. See details in the device BSDL files.
Document Number : 38-06069 Rev. *L
Page 12 of 30
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