CY8C58LP_13 Datasheet, PDF (7/122 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C58LP Family
Datasheet
Figure 2-4. 100-pin TQFP Part Pinout
(TRACEDATA[1], GPIO) P2[5] 1
(TRACEDATA[2], GPIO) P2[6] 2
(TRACEDATA[3], GPIO) P2[7] ₃
(I2C0: SCL, SIO) P12[4] 4
(I2C0: SDA, SIO) P12[5] 5
(GPIO) P6[4] ₆
(GPIO) P6[5] ₇
(GPIO) P6[6] ₈
(GPIO) P6[7] 9
VSSB 10
IND 11
VBOOST ₁₂
VBAT 13
VSSD 14
XRES 15
(GPIO) P5[0] ₁₆
(GPIO) P5[1] ₁₇
(GPIO) P5[2] ₁₈
(GPIO) P5[3] 19
(TMS, SWDIO, GPIO) P1[0] 20
(TCK, SWDCK, GPIO) P1[1] 21
(Configurable XRES, GPIO) P1[2] 22
(TDO, SWV, GPIO) P1[3] 23
(TDI, GPIO) P1[4] 24
(NTRST, GPIO) P1[5] 25
Lines show VDDIO
to I/O supply
association
TQFP
75 VDDIO0
74 P0[3] (GPIO, OPAMP0-, EXTREF0)
73 P0[2] (GPIO, OPAMP0+, SAR1 EXTREF)
72 P0[1] (GPIO, OPAMP0OUT)
71 _{P0[0] (GPIO, OPAMP2OUT)}
70 P4[1] (GPIO)
69 P4[0] (GPIO)
68 P12[3] (SIO)
67 P12[2] (SIO)
66 VSSD
65 VDDA
64 ^VSSA
63 VCCA
62 NC
61 NC
60 NC
59 NC
58 NC
57 NC
56 P15[3] (GPIO, KHZ XTAL: XI)
55 P15[2] (GPIO, KHZ XTAL: XO)
54 ^{P12[1] (SIO, I2C1: SDA)}
53 ^{P12[0] (SIO, I2C1: SCL)}
52 P3[7] (GPIO, OPAMP3OUT)
51 _{P3[6] (GPIO, OPAMP1OUT)}
Figure 2-5 on page 8 and Figure 2-6 on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part,
for optimal analog performance on a two-layer board.
■ The two pins labeled VDDD must be connected together.
■ The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and “Power System”
section on page 24. The trace between the two VCCD pins should be as short as possible.
■ The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84932 Rev. *C
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