CY8C58LP_13 Datasheet, PDF (1/122 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C58LP Family
Datasheet
Programmable System-on-Chip (PSoC^®)
General Description
With its unique array of configurable blocks, PSoC^® 5LP is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C58LP family is also a high-performance configurable digital system with
some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN).
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I/O pins, and
a rich library
of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP
family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute
design changes through simple firmware updates.
Features
■ 32-bit ARM Cortex-M3 CPU core
❐ DC to 67 MHz operation
❐ Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention, and multiple security features
❐ Up to 32-KB flash error correcting code (ECC) or configura-
tion storage
❐ Up to 64 KB SRAM
❐ 2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 M cycles, and 20 years retention
❐
2A4H-Bch_[1a_] nbnuesl
direct memory
access
access
(DMA)
with
multilayer
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
■ Low voltage, ultra low power
❐ Wide operating voltage range: 0.5 V to 5.5 V
❐ High-efficiency boost regulator from 0.5 V input to 1.8 V to
5.0 V output
❐ 3.1 mA at 6 MHz
❐ Low power modes including:
• 2-µA sleep mode with real time clock (RTC) and low-volt-
age detect (LVD) interrupt
• 300-nA hibernate mode with RAM retention
■ Versatile I/O system
❐ 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs^[2])
❐ Any GPIO to any digital or analog peripheral routability
❐ LCD direct drive from any GPIO, up to 46×16 segments
❐ CapSense^® support from any GPIO^[3]
❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains
❐ Maskable, independent IRQ on any pin or port
❐ Schmitt-trigger transistor-transistor logic (TTL) inputs
❐ All GPIOs configurable as open drain high/low,
pull-up/pull-down, High-Z, or strong output
❐ Configurable GPIO pin state at power-on reset (POR)
❐ 25 mA sink on SIO
❐ Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
■ Analog peripherals (1.71 V ≤ V_DDA ≤ 5.5 V)
❐ 1.024 V ±0.1% internal voltage reference across –40°C to
+85°C
❐ Configurable delta-sigma ADC with 8- to 20-bit resolution
• Sample rates up to 192 ksps
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL
❐ Up to two SAR ADCs, each 12-bit at 1 Msps
❐ Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs
❐ Four comparators with 95-ns response time
❐ Four uncommitted opamps with 25-mA drive capability
❐ Four configurable multifunction analog blocks. Example con-
figurations are programmable gain amplifier (PGA), tran-
simpedance amplifier (TIA), mixer, and sample and hold
❐ CapSense support
■ Programming, debug, and trace
❐ JTAG (4 wire), serial wire debug (SWD) (2 wire), single wire
viewer (SWV), and TRACEPORT interfaces
❐ Cortex-M3 flash patch and breakpoint (FPB) block
❐ Cortex-M3 Embedded Trace Macrocell™ (ETM™) gener-
ates an instruction trace stream.
❐ Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
❐ Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
used for printf-style debugging
❐ DWT, ETM, and ITM blocks communicate with off-chip debug
and trace systems via the SWV or TRACEPORT
❐ Bootloader programming supportable through I²C, SPI,
UART, USB, and other interfaces
■ Digital peripherals
❐ 20 to 24 programmable logic device (PLD) based universal
digital blocks (UDBs)
❐ Full CAN 2.0b 16 RX, 8 TX buffers^[2]
❐ Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator^[2]
❐ Four 16-bit configurable timers, counters, and PWM blocks
❐ 67-MHz, 24-bit fixed point digital filter block (DFB) to
implement finite impulse response (FIR) and infinite impulse
response (IIR) filters
❐ Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
•
Serial peripheral interface (SPI),
transmitter receiver (UART), and
uI₂nCiversal
asynchronous
• Many others available in catalog
■ Precision, programmable clocking
❐ 3- to 62-MHz internal oscillator over full temperature and volt-
age range
❐ 4- to 25-MHz crystal oscillator for crystal PPM accuracy
❐ Internal PLL clock generation up to 67 MHz
❐ 32.768-kHz watch crystal oscillator
❐ Low power internal oscillator at 1, 33, and 100 kHz
■ Temperature and packaging
❐ –40 °C to +85 °C degrees industrial temperature
❐ 68-pin QFN and 100-pin TQFP package options.
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 115 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-84932 Rev. *C
• 198 Champion Court
•
, San Jose CA 95134-1709
•
408-943-2600
Revised March 1, 2013