CY7C1517V18 Datasheet, PDF (7/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 4-Word Burst Architecture

CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
Pin Definitions (continued)
Pin Name
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
V_SS/144M
V_SS/288M
V_REF
V_DD
V_SS
V_DDQ
I/O
Pin Description
Clock Output CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Clock Output _{CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input}
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q_[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V_DD, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
Input
DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
Output TDO for JTAG.
Input
TCK pin for JTAG.
Input
TDI pin for JTAG.
Input
TMS pin for JTAG.
N/A
Not connected to the die. Can be tied to any voltage level.
Input
Address expansion for 144M. Can be tied to any voltage level.
Input
Address expansion for 288M. Can be tied to any voltage level.
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
Reference as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1517V18, CY7C1528V18, CY7C1519V18, and
CY7C1521V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks (C/C or
K/K when in single-clock mode).
All synchronous data inputs (D_[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q_[x:0]) pass through
output registers controlled by the rising edge of the output
clocks (C/C or K/K when in single clock mode).
All synchronous control (R/W, LD, BWS_[0:X]) inputs pass
through input registers controlled by the rising edge of the
input clock (K).
CY7C1519V18 is described in the following sections. The
same basic descriptions apply to CY7C1517V18,
CY7C1528V18 and CY7C1521V18.
Read Operations
The CY7C1519V18 is organized internally as a 4M x 18
SRAM. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the Address inputs is
stored in the Read address register and the least two signif-
icant bits of the address are presented to the burst counter.
The burst counter increments the address in a linear fashion.
Following the next K clock rise the corresponding 18-bit word
of data from this address location is driven onto the Q_[17:0]
using C as the output timing reference. On the subsequent
rising edge of C the next 18-bit data word from the address
location generated by the burst counter is driven onto the
Q_[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q_[17:0]. The requested data will be
valid 0.45 ns from the rising edge of the output clock (C or C,
or K or K when in single clock mode, 300-MHz, 250-MHz and
200-MHz device). In order to maintain the internal logic, each
Read access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes two clock cycles
to complete. Therefore, Read accesses to the device can not
be initiated on two consecutive K clock rises. The internal logic
of the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C/C or
K/K when in single-clock mode).
When read access is deselected, the CY7C1519V18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically tri-state the outputs following the
next rising edge of the positive output clock (C). This will allow
Document #: 38-05565 Rev. *E
Page 7 of 28