CY7C1517V18 Datasheet, PDF (23/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 4-Word Burst Architecture

CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
Switching Characteristics Over the Operating Range (continued)^{[23, 24]}
Cypress Consortium
Parameter Parameter
Description
300 MHz 278 MHz 250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Output Times
t_CO
t_CHQV
C/C Clock Rise
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
(or K/K in single clock mode)
to Data Valid
t_DOH
t_CHQX
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
t_CCQO
t_CHCQV
C/C Clock Rise to Echo
Clock Valid
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
t_CQOH
t_CHCQX
Echo Clock Hold after C/C –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
Clock Rise
t_CQD
t_CQDOH
t_CHZ
t_CQHQV
t_CQHQX
t_CHQZ
t_CLZ
t_CHQX1
DLL Timing
t_{KC Var}
t_{KC lock}
t_{KC Reset}
t_{KC Var}
t_{KC lock}
t_{KC Reset}
Echo Clock High to Data
Valid
Echo Clock High to Data
Invalid
Clock (C and C) Rise to
High-Z
(Active to High-Z)^{[27, 28]}
Clock (C and C) Rise to
Low-Z^{[27, 28]}
– 0.27 – 0.27 – 0.30 – 0.35 – 0.40 ns
–0.27 – –0.27 – –0.30 – –0.35 – –0.40 – ns
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
– 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
1024 – 1024 – 1024 – 1024 – 1024 – Cycles
30
30
30
30
30
ns
Notes:
27. t_CHZ, t_CLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
28. At any given voltage and temperature t_CHZ is less than t_CLZ and t_CHZ less than t_CO.
Document #: 38-05565 Rev. *E
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