CY7C1517V18 Datasheet, PDF (6/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 4-Word Burst Architecture

CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
Pin Definitions
Pin Name
I/O
Pin Description
DQ_[x:0]
LD
Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When Read access is deselected, Q_[x:0] are automatically tri-stated.
CY7C1517V18 - DQ_[7:0]
CY7C1528V18 - DQ_[8:0]
CY7C1519V18 - DQ_[17:0]
CY7C1521V18 - DQ_[35:0]
Input- Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and read/write direction. All transactions operate on a burst of 4
data (two clock periods of bus activity).
NWS₀, NWS₁
Input-
Synchronous
Nibble Write Select 0, 1 − active LOW (CY7C1517V18 only). Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS₀ controls D_[3:0] and NWS₁ controls D_[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS₀, BWS₁,
BWS₂, BWS₃
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1528V18 − BWS₀ controls D_[8:0]
CY7C1519V18− BWS₀ controls D_[8:0] and BWS₁ controls D_[17:9].
CY7C1521V18− BWS₀ controls D_[8:0], BWS₁ controls D_[17:9], BWS₂ controls D_[26:18] and BWS₃
controls D_[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0, A1
Input- Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 8M x 8 (four arrays each of 2M x 8) for CY7C1517V18,
8M x 9 (four arrays each of 2M x 9) for CY7C1528V18, a single 4M x 18 array for CY7C1519V18,
and a single 2M x 36 array for CY7C1521V18.
CY7C1517V18 – Since the least two significant bits of the address internally are “00,” only 21
address inputs are needed to access the entire memory array.
CY7C1528V18 – Since the least two significant bits of the address internally are “00,” only 21
address inputs are needed to access the entire memory array.
CY7C1519V18 – A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 22 address inputs are needed to access the entire memory array.
CY7C1521V18 – A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 21 address inputs are needed to access the entire memory array.
All the address inputs are ignored when write access is deselected.
R/W
Input- Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
C
Input- Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
Clock data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
C
Input- Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
Clock data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K
Input- Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
Clock
device and to drive out data through Q_[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input- Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
Clock
device and to drive out data through Q_[x:0] when in single clock mode.
Document #: 38-05565 Rev. *E
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