CY7C1517V18 Datasheet, PDF (19/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 4-Word Burst Architecture

Power-Up Sequence in DDR-II SRAM^{[14, 15]}
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
— Apply V_DD before V_DDQ
— Apply V_DDQ before V_REF or at the same time as V_REF
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock.
Power-up Waveforms
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
DLL Constraints
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
t_{KC Var}.
• The DLL will function at frequencies down to 80 MHz.
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior.
K
K
V_DD/ V_DDQ
Unstable Clock
> 1024 Stable clock
Clock Start (Clock Starts after V_DD / V_DDQ Stable)
V_DD / V_DDQ Stable (< +/- 0.1V DC per 50ns )
DOFF
Fix High (or tied to VDDQ)
Notes:
14. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
15. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Start Normal
Operation
Document #: 38-05565 Rev. *E
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