CYRF69103_13 Datasheet, PDF (61/72 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69103
AC Characteristics
Parameter
Description
GPIO Timing
T_{R_GPIO} Output Rise Time
T_{F_GPIO} Output Fall Time
F_IMO
Internal Main Oscillator Frequency
F_ILO
Internal Low Power Oscillator
SPI Timing
T_SMCK
T_SSCK
T_SCKH
T_SCKL
T_MDO
T_MDO1
SPI Master Clock Rate
SPI Slave Clock Rate
SPI Clock High Time
SPI Clock Low Time
Master Data Output Time^[18]
Master Data Output Time,
First bit with CPHA = 0
T_MSU
T_MHD
T_SSU
T_SHD
T_SDO
T_SDO1
Master Input Data Setup time
Master Input Data Hold time
Slave Input Data Setup Time
Slave Input Data Hold Time
Slave Data Output Time
Slave Data Output Time,
First bit with CPHA = 0
T_SSS
T_SSH
Slave Select Setup Time
Slave Select Hold Time
Conditions
Min
Typ
Measured between 10 and 90%
Vdd/Vreg with 50 pF load
–
–
Measured between 10 and 90%
Vdd/Vreg with 50 pF load
–
–
With proper trim values loaded^[5]
18.72
–
With proper trim values loaded^[5] 15.0001 –
F_CPUCLK/6
–
–
–
–
High for CPOL = 0, Low for CPOL = 1 125
–
Low for CPOL = 0, High for CPOL = 1 125
–
SCK to data valid
–25
–
Time before leading SCK edge
100
–
50
–
50
–
50
–
50
–
SCK to data valid
–
–
Time after SS LOW to data valid
–
–
Before first SCK edge
After last SCK edge
150
–
150
–
Figure 19. Clock Timing
T_CH
T_CYC
Max Unit
50
ns
15
ns
26.4 MHz
50.0 kHz
2
MHz
2.2 MHz
–
ns
–
ns
50
ns
–
ns
–
ns
–
ns
–
ns
–
ns
100
ns
100
ns
–
ns
–
ns
CLOCK
T_CL
Note
18. In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
Document Number: 001-07611 Rev *I
Page 61 of 72