CYRF69103_13 Datasheet, PDF (51/72 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69103
Figure 17. Memory Mapped Registers Read/Write Timing Diagram
clk_sys
rd_wrn
Valid
Addr
rdata
wdata
Memory mapped registers Read/Write timing diagram
Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the CYRF69103 devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually. The registers also provide
a mechanism by which a user may clear all pending and posted
interrupts, or clear individual posted or pending interrupts.
The following table lists all interrupts and the priorities that are
available in the CYRF69103.
Table 68. Interrupt Priorities, Address, Name
Interrupt
Priority
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Interrupt
Address
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
0020h
0024h
0028h
002Ch
0030h
0034h
0038h
003Ch
Name
Reset
POR/LVD
Reserved
SPI Transmitter Empty
SPI Receiver Full
GPIO Port 0
GPIO Port 1
INT1
Reserved
Reserved
Reserved
Reserved
Reserved
1 ms Interval timer
Programmable Interval Timer
Reserved
Table 68. Interrupt Priorities, Address, Name (continued)
Interrupt
Priority
16
17
18
19
20
21
22
23
24
25
Interrupt
Address
0040h
0044h
0048h
004Ch
0050h
0054h
0058h
005Ch
0060h
0064h
Name
Reserved
16-bit Free Running Timer Wrap
INT2
Reserved
GPIO Port 2
Reserved
Reserved
Reserved
Reserved
Sleep Timer
Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in Figure 18 on page 52 clocking in a ‘1’.
The interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It simply prevents a
posted interrupt from becoming pending.
Nested interrupts can be accomplished by reenabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register.
A block diagram of the CYRF69103 Interrupt Controller is shown
in Figure 18 on page 52.
Document Number: 001-07611 Rev *I
Page 51 of 72