CYRF69103_13 Datasheet, PDF (11/72 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69103
Figure 5. PMU Disabled - External Boost Converter
VCC
External DC-DC
VBat
Boost Converter
1 Ohm 1%
47 Ohm
10µF
6.3V
1µF
6.3V
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
VDD
VDD_MICRO
0.1µF
PRoC LP
Low Noise Amplifier (LNA) and Received Signal
Strength Indication (RSSI)
The gain of the receiver may be controlled directly by clearing
the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit
of the RX_CFG_ADR register. When the LNA bit is cleared, the
receiver gain is reduced by approximately 20 dB, allowing
accurate reception of very strong received signals (for example
when operating a receiver very close to the transmitter). An
additional 20 dB of receiver attenuation can be added by setting
the Attenuation (ATT) bit; this allows data reception to be limited
to devices at very short ranges. Disabling AGC and enabling
LNA is recommended unless receiving from a device using
external PA.
The RSSI register returns the relative signal strength of the
on-channel signal power.
When receiving, the device may be configured to automatically
measure and store the relative strength of the signal being
received as a 5-bit value. When enabled, an RSSI reading is
taken and may be read through the SPI interface. An RSSI
reading is taken automatically when the start of a packet is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI register, allowing the
background RF energy level on any given channel to be easily
measured when RSSI is read when no signal is being received.
A new reading can occur as fast as once every 12 s.
Receive Spurious Response
The transmitter may exhibit spurs around 50MHz offset at levels
approximately 50dB to 60dB below the carrier power. Receivers
operating at the transmit spur frequency may receive the spur if
the spur level power is greater than the receive sensitivity level.
The workaround for this is to program an additional byte in the
packet header which contains the transmitter channel number.
After the packet is received, the channel number can be
checked. If the channel number does not match the receive
channel then the packet is rejected.
SPI Interface
The SPI interface between the MCU function and the radio
function is a 3-wire SPI Interface. The three pins are MOSI
(Master Out Slave In), SCK (Serial Clock), SS (Slave Select).
There is an alternate 4-wire MISO Interface that requires the
connection of two external pins. The SPI interface is controlled
by configuring the SPI Configure Register. (SPICR Addr: 0x3D).
3-Wire SPI Interface
The radio function receives a clock from the MCU function on the
SCK pin. The MOSI pin is multiplexed with the MISO pin.
Bidirectional data transfer takes place between the MCU function
and the radio function through this multiplexed MOSI pin. When
using this mode the user firmware must ensure that the MOSI pin
on the MCU function is in a high impedance state, except when
the MCU is actively transmitting data. Firmware must also control
the direction of data flow and switch directions between MCU
function and radio function by setting the SWAP bit [Bit 7] of the
SPI Configure Register. The SS pin is asserted before initiating
a data transfer between the MCU function and the radio function.
The IRQ function may be optionally multiplexed with the MOSI
pin; when this option is enabled the IRQ function is not available
while the SS pin is low. When using this configuration, user
firmware must ensure that the MOSI function on MCU function
is in a high-impedance state whenever SS is high.
Figure 6. 3-Wire SPI Mode
MCU Function
Radio Function
P1.5/MOSI
MOSI
MOSI/MISO multiplexed
on one MOSI pin
P1.4/SCK
SCK
P1.3/nSS
nSS
4-Wire SPI Interface
The 4-wire SPI communications interface consists of MOSI,
MISO, SCK, and SS.
Document Number: 001-07611 Rev *I
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