W230-03 Datasheet, PDF (6/15 Pages) Cypress Semiconductor – Spread Spectrum FTG for VIA K7 Chipset

PRELIMINARY
W230-03
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 5 gives the bit formats for registers located in Data
Bytes 0–7.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 5. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s) Pin No. Pin Name
Control Function
0
Data Byte 0
7
--
--
(Reserved)
--
1
Default
--
0
6
--
5
--
4
--
--
SEL_2
--
SEL_1
--
SEL_0
See Table 6
0
See Table 6
0
See Table 6
0
3
--
--
Hardware/Software Frequency
Hardware
Software
0
Select
2
--
--
SEL_4
See Table 6
1
1
--
--
SEL_3
See Table 6
0
0
--
Data Byte 1
7
--
--
--
(Reserved)
Normal
--
Three-stated
0
--
0
6
--
5
--
4
--
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
--
0
--
--
0
--
--
0
3
--
2
--
1
--
--
(Reserved) Write to ‘1’
--
(Reserved) Write to ‘1’
--
(Reserved) Write to ‘1’
--
--
1
--
--
1
--
--
1
0
--
Data Byte 2
7
--
--
(Reserved) Write to ‘1’
--
(Reserved)
--
--
1
--
--
0
6
7
PCI0
Clock Output Disable
5
--
--
(Reserved)
4
13
PCI5
Clock Output Disable
Low
Active
1
--
--
0
Low
Active
1
3
12
PCI4
Clock Output Disable
2
11
PCI3
Clock Output Disable
1
10
PCI2
Clock Output Disable
Low
Active
1
Low
Active
1
Low
Active
1
0
8
Data Byte 3
7
--
PCI1
Clock Output Disable
--
(Reserved)
Low
Active
1
--
--
0
6
--
SEL_48MHz SEL 48MHz as the output fre-
quency for 24_48MHz
5
26
48MHz Clock Output Disable
24-MHz
Low
48-MHz
0
Active
1
4
25
24_48MHz Clock Output Disable
3
--
--
(Reserved)
2
21, 20, SDRAM8:11 Clock Output Disable
18, 17
Low
Active
1
--
--
0
Low
Active
1
Document #: 38-07357 Rev. *A
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