W230-03 Datasheet, PDF (2/15 Pages) Cypress Semiconductor – Spread Spectrum FTG for VIA K7 Chipset

PRELIMINARY
W230-03
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPUT0,
CPUC0,
43, 44
O
CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs
(open-drain) for the K7 processor.
CPU_CS
46
O
CPU Clock Output for Chipset: CPU_CS is the push-pull clock output for the
chipset. It has the same phase relationship as CPUT0.
PCI2:5
10, 11, 12, 13
O
PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by
the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial
input interface, see Tables 2 and 6 for details. Output voltage swing is controlled
by voltage applied to VDDQ3.
PCI1/FS1
8
I/O
Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by
FS0:3 inputs or through serial input interface. This output is controlled by the
PWRDWN# input. This pin also serves as a power-on strap option to determine
device operating frequency as described in Table 2.
PCI0/MODE
7
I/O
Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs
or through serial input interface, see Tables 2 and 6. This output is controlled by
the PWRDWN# input. This pin also serves as a power-on strap option to determine
the function of pin 2, see Table 1 for details.
PWRDWN#
41
I
PWRDWN# Input: LVTTL-compatible input that places the device in power-down
mode when held LOW. In power-down mode, CPUC0 will be three-stated and all
the other output clocks will be driven LOW.
48MHz/FS2
26
I/O
48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In
standard PC systems, this output can be used as the reference for the Universal
Serial Bus host controller. This pin also serves as a power on strap option to
determine device operating frequency as described in Table 2.
24_48MHz/
25
FS3
I/O
24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can
be used as the clock input for a Super I/O chip. The output frequency is controlled
by Configuration Byte 3 bit[6]. The default output frequency is 48 MHz. This pin
also serves as a power-on strap option to determine device operating frequency
as described in Table 2.
REF1/FS0
48
I/O
Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock.
This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 2. Upon power-up, FS0 input will be latched which
will set clock frequencies as described in Table 2.
REF0/
2
CPU_STOP
#
I/O
Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined
by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPUT0
and CPU_CS to logic 0, and it will three-state CPUC0. When this pin is configured
as an output, this pin becomes a 3.3V 14.318-MHz output clock.
SDRAMIN
15
I
Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
SDRAM0:12 38, 37, 35,
O
Buffered Outputs: These thirteen dedicated outputs provide copies of the signal
34, 32, 31,
provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deac-
29, 28, 21,
tivated when PWRDWN# input is set LOW.
20, 18, 17, 40
SCLK
24
I
Clock pin for I²C circuitry.
SDATA
23
I/O
Data pin for I²C circuitry.
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
1, 6, 14, 19,
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
27, 30, 36, 42
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect
to 3.3V supply
GND
3, 9, 16, 22,
G
Ground Connections: Connect all ground pins to the common system ground
33, 39, 45, 47
plane.
Document #: 38-07357 Rev. *A
Page 2 of 15