W230-03 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – Spread Spectrum FTG for VIA K7 Chipset

3
PRELIMINARY
W230-03
Spread Spectrum FTG for VIA K7 Chipset
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for VIA K7
chipset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
• I²C™ interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V_DDQ3: .................................................................... 3.3V±5%
SDRAMIN to SDRAM0:12 Delay: ..........................3.7 ns typ.
Table 1. Mode Input Table
Mode
Pin 2
0
CPU_STOP#
1
REF0
Block Diagram
X1
XTAL
X2
OSC
PLL Ref Freq
I/O Pin
Control
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
PWRDWN#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I²C
Logic
PLL2
÷2
SDRAMIN
I²C is a trademark of Phillips Corporation.
CPU_CS
CPUT0
CPUC0
VDDQ3
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS2
24_48MHz/FS3
VDDQ3
SDRAM0:12
13
Table 2. Pin Selectable Frequency
Input Address
CPU_CS
CPUT0
FS3 FS2 FS1 FS0 (MHz)
1111
100.0
1110
100.0
1101
100.0
1100
95.0
1011
133.3
1010
133.3
1001
133.3
1000
102.0
0111
104.0
0110
106.0
0101
107.0
0100
108.0
0011
109.0
0010
110.0
0001
111.0
0000
112.0
PCI 0:5
(MHz)
33.3
33.3
33.3
31.7
33.3
33.3
33.3
34.0
34.6
35.3
35.6
36.0
36.3
36.6
37.0
37.3
Spread
Spectrum
–0.5%
OFF
±0.5%
OFF
–0.5%
OFF
±0.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Pin Configuration^[1]
VDDQ3 1
REF0/(CPU_STOP#) 2
GND 3
X1 4
X2 5
VDDQ3 6
PCI0/MODE 7
PCI1/FS1* 8
GND 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
VDDQ3 14
SDRAMIN 15
GND 16
SDRAM11 17
SDRAM10 18
VDDQ3 19
SDRAM9 20
SDRAM8 21
GND 22
{ I2C SDATA 23
SCLK 24
48 REF1/FS0*
47 GND
46 CPU_CS
45 GND
44 CPUC0
43 CPUT0
42 VDDQ3
41 PWRDWN#*
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS2*
25 24_48MHz/FS3^
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07357 Rev. *A
Revised December 26, 2002