W215B Datasheet, PDF (6/14 Pages) Cypress Semiconductor – Uses external 14.318-MHz crystal

PRELIMINARY
W215B
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
f
Frequency, Actual
Measured on rising edge at 1.5V
Determined by PLL divider ratio
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_SK
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
f_ST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequency
stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
CPU = 100 MHz
Min. Typ. Max.
10
100
1
4
1
4
45 50 55
500
100
1.5
3
16
Unit
ns
MHz
V/ns
V/ns
%
ps
ps
ns
ms
Ω
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
t_P
Period
f
Frequency, Actual
t_H
High Time
t_L
Low Time
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
t_JC
Jitter, Cycle-to-Cycle
t_SK
Output Skew
t_O
CPU to PCI Clock Skew
f_ST
Frequency Stabilization
from Power-up (cold
start)
Z_o
AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
CPU = 100 MHz
Min. Typ. Max.
30
33.3
12
12
1
4
1
4
45 50 55
500
250
1
4
3
15
Unit
ns
MHz
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
Document #: 38-07222 Rev. *A*
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