W215B Datasheet, PDF (5/14 Pages) Cypress Semiconductor – Uses external 14.318-MHz crystal

PRELIMINARY
W215B
DC Electrical Characteristics (continued)
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5% (3.135–3.465V), f_XTL = 14.31818 MHz, V_DDQ2 = 3.3V±5%
Parameter
Description
Test Condition
Min. Typ. Max. Unit
Crystal Oscillator
V_TH
X1 Input Threshold Voltage^[4]
C_LOAD
Load Capacitance, Imposed on External
Crystal^[5]
C_IN,X1
X1 Input Capacitance^[6]
Pin Capacitance/Inductance
V_DDQ3 = 3.3V
Pin X2 unconnected
1.65
V
14
pF
28
pF
C_IN
Input Pin Capacitance
Except X1 and X2
5
pF
C_OUT
Output Pin Capacitance
6
pF
L_IN
Input Pin Inductance
7
nH
Notes:
4. X1 input threshold voltage (typical) is V_DDQ3/2.
5. The W215B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics (Lump Load Model)
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5% (3.135–3.465V) f_XTL = 14.31818 MHz, V_DDQ2 = 3.3V±5%
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
Test Point
FTG
*20pF for CPU, REF1, IOAPIC,
24MHz & 48MHz
*30pF for SDRAM & PCI
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
Parameter
t_P
f
t_H
t_L
t_R
t_F
t_D
t_JC
t_SK
f_ST
Z_o
Description
Period
Frequency, Actual
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Output Skew
Frequency Stabilization from
Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
CPU = 100 MHz
Min. Typ. Max.
10
100
5
5
1
4
1
4
45 50 55
500
250
3
10
Unit
ns
MHz
ns
ns
V/ns
V/ns
%
ps
ps
ms
Ω
Document #: 38-07222 Rev. *A*
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