W215B Datasheet, PDF (2/14 Pages) Cypress Semiconductor – Uses external 14.318-MHz crystal

PRELIMINARY
W215B
Pin Definitions
Pin
Pin Name
No.
CPU0:3
42, 41, 39,
38
PCI0:5
9, 11, 12, 13,
14, 16
PCI_F
8
SDRAM0:5
36, 35, 33,
32, 30, 29
SDRAM6/
27
CPU_STOP#
SDRAM7/
26
PCI_STOP#
IOAPIC
48/24MHz
45
22, 23
REF0:1
2, 1
CPU_2.5#
47
95/100_SEL
18
X1
4
X2
5
Pin
Type
O
O
O
O
I/O
I/O
O
O
O
I
I
I
I
Pin Description
CPU Outputs 0 through 3: These four CPU outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2.
PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchro-
nous to the CPU clock outputs. Output voltage swing is controlled by voltage applied
to VDDQ3.
SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual
functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the
CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6.
Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3
are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When
brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (2–3
CPU clock latency).
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual
functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the
PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7.
PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after
completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started
beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI
clock following PCI_STOP# state change.
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device
power-up. Either or both can be changed to 24 MHz through use of the serial data
interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied
to VDDQ3
Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Out-
put voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than
REF1 and should be used for driving ISA slots.
Set to logic 1 for 3.3V CPU I/O.
95- or 100-MHz Input Selection: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selec-
tions).
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Document #: 38-07222 Rev. *A*
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