W150 Datasheet, PDF (6/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W150
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–5 Serial Configuration Map
Affected Pin
Bit(s) Pin No. Pin Name
Control Function
Data Byte 0
7
--
--
(Reserved)
6
--
--
SEL_2
5
--
--
SEL_1
4
--
--
SEL_0
Bit Control
0
1
--
--
See Table 6
See Table 6
See Table 6
Default
0
0
0
0
3
--
--
Frequency Table Selection
Frequency Con- Frequency Con-
0
trolled by FS (3:0) trolled by SEL (3:0)
Table 2
Table 6
2
--
--
SEL3
Refer to Table 6
0
1–0
--
--
Bit 1 Bit 0 Function (See Table 7 for function details)
00
0
0 Normal Operation
0
1 (Reserved)
1
0 Spread Spectrum On
1
1 All Outputs Three-stated
Data Byte 1
7
--
--
--
--
--
0
6
--
--
--
--
--
0
5
--
--
--
--
--
0
4
--
--
--
--
--
0
3
46
SDRAM_F Clock Output Disable
Low
Active
1
2
49
CPU2
Clock Output Disable
Low
Active
1
1
51
CPU1
Clock Output Disable
Low
Active
1
0
52
CPU_F Clock Output Disable
Low
Active
1
Data Byte 2
7
--
--
(Reserved)
--
--
0
6
8
PCI_F Clock Output Disable
Low
Active
1
5
16
PCI5
Clock Output Disable
Low
Active
1
4
14
PCI4
Clock Output Disable
Low
Active
1
3
13
PCI3
Clock Output Disable
Low
Active
1
2
12
PCI2
Clock Output Disable
Low
Active
1
1
11
PCI1
Clock Output Disable
Low
Active
1
0
9
PCI0
Clock Output Disable
Low
Active
1
Data Byte 3
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
29
48MHz Clock Output Disable
Low
Active
1
4
30
24MHz Clock Output Disable
Low
Active
1
6