W150 Datasheet, PDF (5/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W150
Serial Data Interface
The W150 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W150 initializes with
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
chipset. If needed, clock device register changes are normally
made upon system initialization. The interface can also be
used during system operation for power management func-
tions. Table 3 summarizes the control functions of the serial
data interface.
Operation
Data is written to the W150 in eleven bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
CPU Clock Frequency
Selection
Spread Spectrum
Enabling
Output Three-state
Test Mode
(Reserved)
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Enables or disables spread spectrum clocking.
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
For EMI reduction.
Puts clock output into a high-impedance state.
All clock outputs toggle in relation to X1 input, in-
ternal PLL is bypassed. Refer to Table 5.
Reserved function for future device revision or
production device testing.
Production PCB testing.
Production PCB testing.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
2
Command Code Don’t Care
3
Byte Count
Don’t Care
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
Refer to Table 5
Don’t Care
Byte Description
Commands the W150 to accept the bits in Data Bytes 0–7 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W150 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W150, therefore bit values are ignored (“don’t care”).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
Unused by the W150, therefore bit values are ignored (“don’t care”).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
The data bits in Data Bytes 0–5 set internal W150 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map.
Unused by the W150, therefore bit values are ignored (don’t care).
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