W150 Datasheet, PDF (12/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W150
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 22 pF)
CPU = 66.8 MHz CPU = 100 MHz
Parameter
t
P
t_H
t_L
t_R
t_F
t_D
Description
Period
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at
1.5V
Min. Typ. Max. Min. Typ. Max. Unit
15
15.5 10
10.5 ns
5.2
3.0
ns
5.0
2.0
ns
1
41
4 V/ns
1
41
4 V/ns
45
55 45
55 %
t_SK
Output Skew
Measured on rising and falling edge at
250
250 ps
1.5V
t_PD
Propagation Delay
Measured from SDRAMIN
3.7
Z_o
AC Output Impedance Average value during switching transi-
15
tion. Used for determining series termi-
nation value.
3.7
ns
15
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
f_D
Deviation from 48 MHz (48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
+167
ppm
57/17
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold
power-up. Short cycles exist prior to frequency stabiliza-
start)
tion.
2 V/ns
2 V/ns
55 %
3 ms
Z_o
AC Output Impedance Average value during switching transition. Used for de-
25
Ω
termining series termination value.
12