SM560 Datasheet, PDF (6/8 Pages) Cypress Semiconductor – Spread Spectrum Clock Generator

SM560 Application Schematic
3.3 uH.
L1
NOTE 1.
SM560
Application Load
C2
27 pF
Y1
40 MHz
VDD
1 _Xin/CLK
2
VDD
C5
22 uF.
C6
0.1 uF
3
GND
R5
4 _SSCLK
22
SM560
Xout ⁸
7
S0
S1 ⁶
SSCC ⁵
C3
27 pF
C4
.01 uF.
VDD
VDD
R2
20 K
R4
20 K
Figure 3. Application Schematic^[2]
The schematic in Figure 3 above demonstrates how the
SM560 is configured in a typical application. This application
is using a 40-MHz reference derived from a third overtone
crystal connected to pins 1 and 8. Since Y1 is a third overtone
crystal a notch filter is created with L1 and C3 to dampen the
gain of the oscillator at the fundamental frequency of this
crystal which is 13.33 MHz.
Figure 3 also demonstrates how to properly use the tri-level
logic employed in the SM560. Notice that resistors R2 and R4
create a voltage divider that places V_DD/2 on pin 7 to satisfy
the voltage requirement for an “M” state.
With this configuration, the SM560 will produce an SSCG
clock that is at a center frequency of 40 MHz. Referring to
Table 2, range “0, M” at 40 MHz will generate a modulation
profile that has a 1.7% peak to peak spread.
Ordering Information^[3]
Part Number
IMISM560BZ
IMISM560BZT
Lead Free Devices
CYISM560BSXC
CYISM560BSXCT
Package Type
8-pin SOIC
8-pin SOIC–Tape and Reel
8-pin SOIC
8-pin SOIC–Tape and Reel
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Marking: Example:
IMI
SM560BS
Date Code, Lot#
SM560 B S
Package
S = SOIC
Revision
IMI Device Number
Note:
2. The value of L1 is calculated such that L1 and C3 are tuned to a frequency that is 130% higher than the fundamental frequency of the crystal.
ZC1 = 1/2πfC
ZC1 = 1/6.28 (17.33 MHz) (27 pF)
ZC1 = 340Ω
ZL1 = 2πFL
L = ZL1/2πf
L = 340/6.28(17.33 MHz)
L = 3.12 µH
3. The ordering part number differs from the marking on the actual device.
Document #: 38-07020 Rev. *E
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