SM560 Datasheet, PDF (4/8 Pages) Cypress Semiconductor – Spread Spectrum Clock Generator

SM560
Absolute Maximum Ratings^[1]
Supply Voltage (V_DD): .................................... –0.5V to +6.0V
DC Input Voltage:..................................–0.5V to VDD + 0.5V
Junction Temperature ................................. –40°C to +140°C
Operating Temperature:...................................... 0°C to 70°C
Storage Temperature .................................. –65°C to +150°C
Static Discharge Voltage (ESD).......................... 2,000V-Min.
Table 2. DC Electrical Characteristics: V_DD = 3.3V, Temp. = 25°C and C_L (Pin 4) = 15 pF, unless otherwise noted
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V_DD
V_INH
V_INM
V_INL
V_OH1
V_OH2
V_OL1
V_OL2
Cin1
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Input Capacitance
±10%
S0 and S1 only
S0 and S1 only
S0 and S1 only
I_OH = 6 mA
I_OH = 20 mA
I_OH = 6 mA
I_OH = 20 mA
Xin/CLK (Pin 1)
2.97
3.3
3.63
V
0.85V_DD
V_DD
V_DD
V
0.40V_DD 0.50V_DD 0.60V_DD
V
0.0
0.0
0.15V_DD
V
2.4
V
2.0
V
0.4
V
1.2
V
3
4
5
pF
Cin2
Input Capacitance
Xout (Pin 8)
6
8
10
pF
Cin2
Input Capacitance
S0, S1, SSCC (Pins 7,6,5)
3
4
5
pF
I_DD1
Power Supply Current
F_IN = 40 MHz
I_DD2
Power Supply Current
F_IN = 65 MHz
30
40
mA
35
45
mA
Table 3. Electrical Timing Characteristics: V_DD = 3.3V, T = 25°C and C_L = 15 pF, unless otherwise noted
Parameter
Description
Conditions
Min.
Typ.
Max.
ICLKFR
Trise
Input Clock Frequency Range
Clock Rise Time (Pin 4)
V_DD = 3.30V
SSCLK1 @ 0.4 – 2.4V
25
108
1.2
1.4
1.6
Tfall
Clock Fall Time (Pin 4)
SSCLK1 @ 0.4 – 2.4V
1.2
1.4
1.6
DTYin
Input Clock Duty Cycle
XIN/CLK (Pin 1)
20
50
80
DTYout
Output Clock Duty Cycle
SSCLK1 (Pin 4)
45
50
55
JCC
Cycle-to-Cycle Jitter
Fin = 25 – 108 MHz
-
125
175
Unit
MHz
ns
ns
%
%
ps
SSCG Theory of Operation
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
The SM560 is a PLL-type clock generator using a proprietary mental and harmonic frequencies, the equipment under test is
Cypress design. By precisely controlling the bandwidth of the able to satisfy agency requirements for EMI. Conventional
output clock, the SM560 becomes a Low EMI clock generator. methods of reducing EMI have been to use shielding, filtering,
The theory and detailed operation of the SM560 will be multi-layer PCBs, etc. The SM560 uses the approach of
discussed in the following sections.
reducing the peak energy in the clock by increasing the clock
EMI
bandwidth, and lowering the Q.
SSCG
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle SSCG uses a patented technology of modulating the clock
that is very close to 50%. Because of this 50/50-duty cycle, over a very narrow bandwidth and controlled rate of change,
digital clocks generate most of their harmonic energy in the both peak and cycle to cycle. The SM560 takes a narrow band
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to digital reference clock in the range of 25–108 MHz and
reduce the amount of energy contained in the fundamental produces a clock that sweeps between a controlled start and
and odd harmonics by increasing the bandwidth of the funda- stop frequency and precise rate of change. To understand
mental clock frequency. Conventional digital clocks have a what happens to a clock when SSCG is applied, consider a
very high Q factor, which means that all of the energy at that 65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
frequency is concentrated in a very narrow bandwidth, conse- know the following:
quently, higher energy peaks. Regulatory agencies test
Note:
1. Single Power Supply: The Voltage on any input or I/O pin cannot exceed the power pin during power up.
Document #: 38-07020 Rev. *E
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