SM560 Datasheet, PDF (3/8 Pages) Cypress Semiconductor – Spread Spectrum Clock Generator

SM560
Tri-level Logic
With binary logic, four states can be programmed with two
control lines, whereas Tri-level Logic can program nine logic
states using two control lines. Tri-level Logic in the SM560 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0.” Pins 6 and 7 of the SM560
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
“1” (One). Each of these states has a defined voltage range
that is interpreted by the SM560 as a “0,” “M,” or “1” logic state.
Refer to Table 2 for voltage ranges for each logic state. By
using two equal value resistors (typically 20K) the “M” state
can be easily programmed. Pins 6 or 7 can be tied directly to
ground or VDD for Logic “0” or “1” respectively.
SM560
VDD = 3.3 VDC
20K
SM560
VDD = 3.3 VDC
SM560
VDD = 3.3 VDC
7 1.65 VDC
7
7
6 0 VDC
20K
6
6
5
5
5
EX. 1
EX. 2
Figure 1.
EX. 3
Document #: 38-07020 Rev. *E
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