CY7C64613 Datasheet, PDF (6/42 Pages) Cypress Semiconductor – EZ-USB FX USB Microcontroller

CY7C64613
1.3 Other Resources
Other sources of EZ-USB FX information include:
• EZ-USB FX Technical Reference Manual (TRM), Version 1.2 or higher
• CY3671 EZ-USB FX Development Kit
• The web site www.cypress.com, which includes information about many Reference Designs, such as USB Mass Storage
Device, ADSL modem, MPEG.2 players, etc.
2.0 Functional Overview
2.1 Microprocessor
The CY7C64613 uses a 12-MHz crystal for low EMI. An internal oscillator and PLL develops an internal 48-MHz clock for use by
the USB Serial Interface Engine and the 8051 microprocessor. The 8051 can run at either 24 MHz or 48 MHz, controlled by a bit
in the EEPROM attached to the I²C-compatible bus. The default rate (with no EEPROM connected) is 24 MHz.
The internal microprocessor is an enhanced version of the industry-standard 8051. Enhancements include four clocks per
instruction cycle operation, a second data pointer, and an enhanced interrupt system. The 8051 includes two UARTS, three
counter-timers, and 256 bytes of register RAM.
The EZ-USB family implements I/O differently than the standard 8051 by having its I/O control registers in external memory space.
The CY7C64613 preserves this addressing for backward EZ-USB compatibility, and adds the ability to control I/O registers using
8051 Special Function Registers (SFRs). This improves I/O access time. For example, an I/O pin may be toggled using one 8051
instruction, e.g., CPL (bit).
The 8051 CODE and XDATA memory consists of an internal 8 KB RAM. This RAM is normally downloaded via the USB cable at
plug-in, followed by the 8051 starting up and executing the downloaded code. This gives the CY7C64613 family its “soft” operation
feature, whereby permanent memory such as ROM or Flash memory is not required. Program code updates can easily be done
in the field since the code is loaded from the PC, not by physically changing or reprogramming a memory device. The 8051
program memory can also be loaded from the EEPROM connected to the I²C compatible bus on reset for stand-alone use without
the USB connected.
The 128-pin version of the CY7C64613 brings out the full 8051 address and data buses, plus decoded control signals OE#, CS#,
RD#, PSEN#, and WR# to allow glueless connection to external memory devices. The 80- and 52-pin packages allow smaller
footprints and more cost effective solutions for certain designs, but do not have external access to the 8051 buses.
2.2 USB SIE
The CY7C64613 uses the EZ-USB family enhanced SIE (Serial Interface Engine). This SIE has the intelligence to perform full
USB enumeration, creating a default USB device with predefined endpoints and alternate settings. This enhanced SIE is essential
in achieving the family’s soft operation, since it provides the mechanism to download firmware prior to the 8051 running.
Once the 8051 is in control, it can use advanced features of the SIE to simplify its USB firmware. Endpoint zero SETUP data is
placed in a separate 8-byte RAM space for easy access. GET_DESCRIPTOR requests are simplified by using a special Setup
Data Pointer. The 8051 simply loads a descriptor address into this 16-bit register, and the SIE takes care of the remaining
overhead, i.e., dividing the descriptor into packets, sending them via endpoint 0 in response to IN tokens, and providing the
necessary handshakes. The 8051 can do other chores while the SIE completes this USB transfer.
2.3 GPIF (General Programmable InterFace)
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable set of vectors that operate similarly to a finite
state machine. It allows the CY7C64613 to perform local bus mastering, and can implement a wide variety of protocols such as
ATAPI, printer parallel port, PCMCIA and Utopia.
The GPIF has six programmable Control Outputs (CTL), six Address Outputs (ADR), and six general purpose Ready Inputs
(RDY). The data bus width can be 8 or 16 bits. Each GPIF instruction defines the state of the control outputs, or determines what
state a ready input (or multiple inputs) must be before proceeding. A sequence of the GPIF instructions make up a single waveform
that will be executed to perform the desired data move between the CY7C64613 and the external circuit.
2.4 Slave FIFOs
Many high-bandwidth USB designs use a FIFO between the USB interface chip and external logic to match data rates, or to
smooth the USB data delivery (which, being packet oriented, occurs in bursts). The CY7C64613 moves this glue logic into the
part by providing four 64-byte internal slave FIFOs. The FIFOs also provide two important interface functions, external clocking
and bus width conversion.
Using external clocking, external logic (such as a DSP or ASIC) can clock data into or out of the slave FIFOs under control of its
own clock, rather than synchronizing with the clock supplied by the CY7C64613 (24 or 48 MHz). The externally supplied clock
Document #: 38-08005 Rev. *B
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