CY7C64613 Datasheet, PDF (17/42 Pages) Cypress Semiconductor – EZ-USB FX USB Microcontroller

CY7C64613
3.3 CY7C64613 Pin Descriptions (continued)
128 80
30 16
52
Name
11 PA5 or
FRD# or
RDY5 or
SLRD
31 17
PA6 or
RxD0OUT
32 18
PA7 or
RxD1OUT
Port B
79 47 29 PB0 or
T2 or
D[0] or
GDA[0] or
AFI [0]
80 48 30 PB1 or
T2EX or
D[1] or
GDA[1] or
AFI [1]
81 49 31 PB2 or
RxD1 or
D[2] or
GDA[2] or
AFI [2]
Type
I/O/Z
I/O/Z
I/O/Z
Default
Description
I
(PA5)
Multiplexed pin whose function is selected by the following bits:
PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FRD# is the write strobe output for an external FIFO connected to the
data bus D[7..0].
RDY5 is a GPIF input signal.
SLRD is the read strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
If the FRD# pin is used, it should be externally pulled up to V_CC. This
is to ensure that FRD# is inactive (pulled HIGH) at power up, since,
before the 8051 can configure this pin to FRD#, it defaults to ‘PA5 an
input’.
I
(PA6)
Multiplexed pin whose function is selected by the PORTACFG.6 bit.
PA6 is a bidirectional I/O port pin.
RxD0OUT is an active-HIGH signal from 8051 UART0.
If RxD0OUT is selected and UART0 is in mode 0, this pin provides the
output data for UART0 only when it is in sync mode. Otherwise it is a 1.
I
(PA7)
Multiplexed pin whose function is selected by the PORTACFG.7 bit.
PA7 is a bidirectional I/O port pin.
RxD1OUT is an active-HIGH output from 8051 UART1.
When RxD1OUT is selected and UART1 is in mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In modes 1,
2, and 3, this pin is HIGH.
I/O/Z
I/O/Z
I/O/Z
I
(PB0)
I
(PB1)
I
(PB2)
The following descriptions apply to the PORT B pins:
D[7..0] is the bidirectional 8051 data bus.
GDA[7..0] is the bidirectional GPIF A data bus.
AFI[7..0] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.0 and IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides
the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does not use
this pin.
D[0] is the bidirectional 8051 data bus, bit 0.
GDA[0] is the bidirectional GPIF A data bus, bit 0.
AFI [0] is the bidirectional A-FIFO data bus, bit 0.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.1 and IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX reloads
timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set
in T2CON.
D[1] is the bidirectional 8051 data bus, bit 1.
GDA[1] is the bidirectional GPIF A data bus, bit 1.
AFI [1] is the bidirectional A-FIFO data bus, bit 1.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.2 and IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
RxD1 is an active-HIGH input signal for 8051 UART1, which provides
data to the UART in all modes.
D[2] is the bidirectional 8051 data bus, bit 2.
GDA[2] is the bidirectional GPIF A data bus, bit 2.
AFI [2] is the bidirectional A-FIFO data bus, bit 2.
Document #: 38-08005 Rev. *B
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