CY7C67200_13 Datasheet, PDF (52/92 Pages) Cypress Semiconductor – EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller

CY7C67200
Register Description
The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. This register must be loaded
with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When
read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the
transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits must be written as ‘0’.
HSS Transmit Address Register [0xC07C] [R/W]
Figure 54. HSS Transmit Address Register
Bit #
15
14
13
12
11
10
9
8
Field
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register Description
The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
HSS Transmit Counter Register [0xC07E] [R/W]
Figure 55. HSS Transmit Counter Register
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Counter...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Counter
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Document Number: 38-08014 Rev. *I
Page 52 of 92