CY8C52_1106 Datasheet, PDF (50/95 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 40 MHz operation

PRELIMINARY
PSoC^® 5: CY8C52 Family Datasheet
Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer
V_DD
Host Programmer
V_DD
SWDCK
SWDIO
XRES
PSoC 5
V_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3 ^{1, 2, 3}
SWDCK (P1[1] or P15[7]) ⁴
SWDIO (P1[0] or P15[6])
XRES
GND
GND
V_SSD, V_SSA
1 _{The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be}
the same. XRES pin is powered by V_DDIO1. The USB SWD pins are powered by V_DDD. So for
programming using the USB SWD pins with XRES pin, the V_DDD, V_DDIO1 of PSoC 5 should be at the same voltage
level as Host V_DD. Rest of PSoC 5 voltage domains (V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same voltage
level as host Programmer. The Port 1 SWD pins are powered by V_DDIO1. So V_DDIO1 of PSoC 5 should be at same
voltage level as host V_DD for Port 1 SWD programming. Rest of PSoC 5 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2,
V_DDIO3) need not be at the same voltage level as host Programmer.
2 _{Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.}
3 _{For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have}
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require
external interface circuitry to toggle power which will depend on the programming setup. The power
supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or
equal to all other supplies.
4 _{When USB SWD pins are used for Programming, the P1[1] SWDCK pin must be externally connected to Ground}
using external pull-down resistor (around 100 K resistor). This is required for P15[7] SWDCK signal to be seen by
PSoC 5's internal logic.
Document Number: 001-66236 Rev. *A
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